Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to integrated memory circuits in silicon technology.
FIG. 1 shows a diagrammatic sectional illustration of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto.
In FIG. 1, reference symbol 1 designates a silicon semiconductor substrate. Provided in the semiconductor substrate 1 are trench capacitors GK1, GK2 having trenches G1, G2, the electrically conductive fillings 20a, 20b of which form first capacitor electrodes. The conductive fillings 20a, 20b are insulated in the lower and central trench region by a dielectric 30a, 30b from the semiconductor substrate 1, which, for its part, forms the second capacitor electrodes (if appropriate in the form of a buried plate (not shown)).
Provided in the central and upper region of the trenches G1, G2 are peripheral insulation collars 10a, 10b, above which are provided buried contacts 15a, 15b, which are in electrical contact with the conductive fillings 20a, 20b and the adjoining semiconductor substrate 1. The buried contacts 15a, 15b are connected to the semiconductor substrate 1 only on one side (cf. FIGS. 2a, b). Insulation regions 16a, 16b insulate the other side of the substrate from the buried contacts 15a, 15b or insulate the buried contacts 15a, 15b toward the top side of the trenches G1, G2.
This enables a very high packing density of the trench capacitors GK1, GK2 and of the associated selection transistors, which will now be explained. In this case, reference is made principally to the selection transistor which is associated with the trench capacitor GK2, since only the drain region D1 or the source region S3, respectively, of adjacent selection transistors is depicted. The selection transistor associated with the trench capacitor GK2 has a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected via a bit line contact BLK to a bit line (not shown) arranged above an insulation layer I. The drain region D2 is connected to the buried contact 15b on one side. A word line WL2 having a gate stack GS2 and a gate insulator G12 surrounding the latter runs above the channel region K2. The word line WL2 is an active word line for the selection transistor of the trench capacitor GK2.
Running parallel adjacent to the word line WL2 are word lines WL1 comprising gate stack GS1 and gate insulator GI1 and word line WL3 comprising gate stack GS3 and gate insulator GI3, which are passive word lines for the selection transistor of the trench capacitor GK2.
Said word lines WL1, WL3 serve for driving selection transistors which are displaced in the third dimension with respect to the sectional illustration shown.
FIG. 1 illustrates the fact that this type of connection on one side of the buried contact enables the trenches and the adjacent source regions or drain regions of relevant selection transistors to be arranged directly beside one another. As a result, the length of a memory cell may amount to just 4 F and the width to just 2 F, where F is the minimum length unit that can be realized technologically (cf. FIGS. 2a, b).
FIG. 2A shows a plan view of a memory cell array with memory cells in accordance with FIG. 1 in a first arrangement possibility.
Reference symbol DT in FIG. 2A designates trenches which are arranged row-wise at a distance of 3 F from one another and columnwise at a distance of 2 F. Adjacent rows are displaced by 2 F relative to one another. UC in FIG. 2A designates the area of a unit cell, which amounts to 4 F×2 F=8 F2. STI designates isolation trenches which are arranged at a distance of 1 F from one another in the row direction and insulate adjacent active regions from one another. Bit lines BL likewise run at a distance of 1 F from one another in the row direction, whereas the word lines run at a distance of 1 F from one another in the column direction. In this arrangement example, all the trenches DT have a contact region KS of the buried contact to the substrate on the left-hand side and an insulation region IS on the right-hand side (regions 15a, b and 16a, b, respectively, in FIG. 1).
FIG. 2B shows a plan view of a memory cell array with memory cells in accordance with FIG. 1 in a second arrangement possibility.
In this second arrangement possibility, the rows of trenches have alternating connection regions and insulation regions of the buried contacts, respectively. Thus, in the bottommost row of FIG. 2B, the buried contacts are in each case provided with a contact region KS1 on the left-hand side and with an insulation region IS1 on the right-hand side. By contrast, in the row located above that, all the trenches DT are provided with each insulation region IS2 on the left-hand side and with a contact region KS2 on the right-hand side. This arrangement alternates in the column direction.
For DRAM memory devices with trench capacitors in sub-100 nm technologies, the resistance of the trench and of the buried contact are a main contribution to the total RC delay, and thus determine the speed of the DRAM. The relatively low conductivity and the pinch-off, which is produced by an overlay displacement of the STI etching, results in a dramatic increase in the series resistance in the trench.
This problem has been tackled by introducing polysilicon that is highly doped with arsenic, improving the overlay between the active regions and the trench, introducing self-aligned fabrication of a buried contact with a connection on one side and thinning the nitrided contact point of the buried contact. The SiN interface nevertheless significantly increases the series resistance since the charge carriers have to tunnel through the SiN interface.